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fet drive simple sequencers ? ADM6819/adm6820 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features single chip enables power supply sequencing of two supplies on-board charge pump fully enhances n-channel fet adjustable primary supply monitor to 0.618 v delay from primary supply to secondary supply enabled fixed 300 ms delay (ADM6819) capacitor adjustable delay (adm6820) logic/analog driven enable input (ADM6819) ?40c to +85c operating range packaged in small 6-lead sot-23 package pin-to-pin compatibility with max6819/max6820 applications multivoltage systems dual voltage microprocessors/fpgas/asics/dsps network processors telecom and datacom systems pc/server applications functional block diagram v cc2 v cc2 out q1 gate logic v cc2 v fet setv en (ADM6819) - digital/analog setd (adm6820) 0.618v 0.618v gnd r1 r2 v cc1 ADM6819/ adm6820 v cc1 v cc1 fet driver charge pump timer uvlo 0 5133-001 figure 1. general description the ADM6819 and adm6820 are simple power supply sequencers with fet drive capability for enhancing n-channel mosfets. these devices can monitor a primary supply voltage and enable/disable an external n-channel fet for a secondary supply. the ADM6819 has the ability to monitor two supplies. when more than two voltages require sequencing, multiple ADM6819/adm6820 devices can be cascaded to achieve this. the devices operate over a supply range of 2.95 v to 5.5 v. an internal comparator monitors the primary supply using the vset pin. the input to this comparator is externally set via a resistor divider from the primary supply. when the voltage at the vset pin rises above the comparator threshold, an internal charge pump on the gate output enhances the secondary supply fet. the ADM6819 features an enable (en) pin that is fed to the input of an additional comparator and reference circuit. this pin can be used as a digital enable or a secondary power good comparator to monitor a second supply and enables the gate only if both supplies are valid. when both inputs of the internal comparators are above the threshold, a fixed 300 ms timeout occurs before the gate is driven high and the secondary supply is enabled. the adm6820 has only one comparator that is on the setv pin. it also features a timeout period that is adjustable via a single external capacitor on the setd pin. the ADM6819/adm6820 are packaged in small 6-lead sot-23 packages.
ADM6819/adm6820 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing diagrams.............................................................................. 4 absolute maximum ratings............................................................ 6 thermal characteristics .............................................................. 6 esd caution.................................................................................. 6 pin configuration and function descriptions..............................7 typical performance characteristics ..............................................8 theory of operation ...................................................................... 10 setv pin ..................................................................................... 10 en pin.......................................................................................... 10 gate pin .................................................................................... 10 setd pin ..................................................................................... 10 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history 7/06rev. 0: initial version
ADM6819/adm6820 rev. 0 | page 3 of 12 specifications v cc1 or v cc2 = 2.95 v to 5.5 v, t a = ?40c to +85c, unless otherwise noted. typical values are at t a = 25c. 1 table 1. parameter min typ max units conditions v cc1 , v cc2 pins v cc1 or v cc2 must be > 2.95 v operating voltage range, v cc1 or v cc2 0.9 5.5 v v cc1 or v cc2 must be > 2.95 v v cc1 or v cc2 supply current, i cc 350 500 a v cc1 = v cc2 = 3.3 v v cc1 or v cc2 disable mode current 250 a v cc1 = v cc2 = 3.3 v, en = gnd v cc1 or v cc2 slew rate 2 6 v/s ADM6819 1.2/t delay v/s adm6820 3 undervoltage lockout, v uvlo 2.4 2.525 2.65 v v cc falling setv pin setv threshold, v th 0.602 0.618 0.634 v v setv rising, enables gate setv input current 2 10 100 na setv threshold hysteresis ?1 % v setv falling, disables gate setv to gate delay, t delay 240 300 350 ms v setv > v th ; v en > v th (ADM6819) setd pin adm6820 setd ramp current, i setd 300 500 730 na 400 500 600 na t a = 25c setd voltage, v setd 1.295 1.326 1.357 v gate pin gate turn-on time, t on 0.5 1.5 10 ms c gate = 1500 pf, v cc2 = 3.3 v, v gate = 7.8 v gate turn-off time, t off 30 s c gate = 1500 pf, v cc2 = 3.3 v, v gate = 0.5 v gate voltage, v gate 4.5 5.5 6.0 v with respect to v ccx , r gate > 50 m to v ccx 4 4.0 5.0 6 v with respect to v ccx , r gate > 5 m to v ccx 4 8.9 9.4 9.9 v with respect to v ccx , r gate > 50 m to v ccx 5 8.2 8.6 9.1 v with respect to v ccx , r gate > 5 m to v ccx 5 enable pin en input voltage low, v il 0.4 v v cc1 or v cc2 must be > 2.95 v en input voltage high, v ih 2.0 v v cc1 or v cc2 must be > 2.95 v 1 100% production tested at t a = +25c. specifications over temper ature limit are guaranteed by design. 2 guaranteed by design, not production tested. 3 t delay (s) = 2.65 10 6 c set . 4 highest supply pin is represented by v ccx = 2.95 v. 5 highest supply pin is represented by v ccx = 5.5 v.
ADM6819/adm6820 rev. 0 | page 4 of 12 timing diagrams v cc2 v cc2 out q1 gate logic v cc2 v fet setv en 0.618v 0.618v gnd r1 r2 r3 r4 v cc1 ADM6819 v cc1 v cc1 fet driver charge pump uvlo 05133-014 figure 2. ADM6819 solution for validating two supplies before sequencing v setv 10% 10% 90% 0.618v v cc2 + 5.5v (typ) v gate t off t delay (ADM6819 = 300ms, adm6820 = adj) t on 05133-015 figure 3. ADM6819/adm6820 timing diagram using setv for sequencing v en v setv 10% 10% 90% 0.618v 0.618v v cc2 + 5.5v (typ) v gate t off t delay (300ms) t on 0 5133-016 figure 4. ADM6819 timing diagram using en and setv for sequencing
ADM6819/adm6820 rev. 0 | page 5 of 12 v out = 3.0v q2 gate v cc2 setv en/setd gnd r3 r4 v cc1 ADM6819/ adm6820 v out = 3.3v v in = 3.0v q1 gate v cc2 setv en/setd gnd r1 r2 v cc1 ADM6819/ adm6820 v in = 3.3v v out = 5 v v in = 5 v 05133-017 figure 5. ADM6819/adm6820 solution for sequencing three supply rails
ADM6819/adm6820 rev. 0 | page 6 of 12 absolute maximum ratings table 2. parameter rating v cc1 , v cc2 ?0.3 v to +6.0 v setv, setd, en ?0.3 v to +30 v gate ?0.3 v to (v ccx + 11 v) storage temperature ?65c to +150c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 6-lead sot-23 169.5 c/w esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADM6819/adm6820 rev. 0 | page 7 of 12 pin configuration and fu nction descriptions v cc1 1 gnd 2 s et v 3 v cc2 6 gate 5 en 4 ADM6819 top view (not to scale) 05133-002 figure 6. ADM6819 pin configuration v cc1 1 gnd 2 s et v 3 v cc2 6 gate 5 setd 4 05133-003 adm6820 top view (not to scale) figure 7. adm6820 pin configuration table 4. pin function descriptions pin umber d61 d620 nemonic description 1 1 v cc1 supply voltage 1. either v cc1 or v cc2 must be greater than the uvlo to enable external fet drive. 2 2 gnd chip ground pin. 3 3 setv sequenced threshold set. connect to an external resistor divider to set the v cc1 threshold that enables gate turn-on. the internal reference is 0.618 v. 4 C en active-high enable. gate drive is enabled t delay after en is driven high. gate drive is immediately disabled when en is driven lo w. connect this pin to the higher of v cc1 or v cc2 if not used. en is internally identical to setv (0.618 v threshold) and, therefore, can be used as a second supply monitor, enabling two supplies to be validated before sequencing begins. C 4 setd gate delay set input. connect an external capacitor from setd to gnd to adjust the delay from setv > v th to gate turn-on. t delay (s) = 2.652 10 6 c set (f). 5 5 gate gate drive output. gate drives an external n-channel fet to connect v cc2 to the load. gate drive enables t delay after setv exceeds v th and enable is driven high. gate drive is immediately disabled when setv drops below v th or enable is driven low. when enabled, an internal charge pump drives gate above v ccx to fully enhance the external n-channel fet. 6 6 v cc2 supply voltage 2. either v cc1 or v cc2 must be greater than the uvlo to enable the external fet drive.
ADM6819/adm6820 rev. 0 | page 8 of 12 typical performance characteristics 0.50 0.10 ?50 temperature (c) 150 v en = 2v v setv = 2v i cc2 (v cc1 = 3.3v, v cc2 = 5v) i cc1 (v cc1 = 5v, v cc2 = 3.3v) 05133-004 supply current (ma) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 ?25 0 25 50 75 100 125 figure 8. supply current vs. temperature 0.50 0 0 v cc2 (v) 7 v cc1 = 0v v en = 2v v setv = 2v 05133-005 i cc2 (ma) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 123456 figure 9. i cc2 vs. v cc2 0.50 0 0 v cc2 (v) 7 v cc1 = 3.3v v en = 2v v setv = 2v 05133-006 i cc2 (ma) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 123456 figure 10. i cc2 vs. v cc2 0.65 0.58 ?50 150 temperature (c) supply current (ma) 05133-007 0.64 0.63 0.62 0.61 0.60 0.59 ?25 0 25 50 75 100 125 figure 11. supply current vs. temperature 0 06 v cc2 (v) v gate (v) 14 12 10 8 6 4 2 v cc1 = 3.3v v en = 2v v setv = v cc2 05133-008 12345 figure 12. v gate vs. v cc2 0 06 v cc2 (v) v gate (v) 14 12 10 8 6 4 2 v cc1 = 0v v en = 2v v setv = 1v 05133-009 12345 figure 13. v gate vs. v cc2
ADM6819/adm6820 rev. 0 | page 9 of 12 0 06 v cc2 (v) v gate (v) 14 12 10 8 6 4 2 v cc1 = 3.3v v en = 2v v setv = 1v 05133-010 12345 figure 14. v gate vs. v cc2 340 240 ?50 150 temperature (c) t delay (ms) 05133-011 ?25 0 25 50 75 100 125 330 320 310 300 290 280 270 260 250 figure 15. t delay vs. temperature 20s/div v setv v gate 5 v/div c load = 1500pf 0 5133-018 figure 16. gate turn-off time 1ms/div v gate 5 v/div c load = 1500pf 0 5133-019 figure 17. gate turn-on time
ADM6819/adm6820 rev. 0 | page 10 of 12 theory of operation the ADM6819/adm6820 provide local voltage sequencing in multisupply systems. figure 18 and figure 19 show typical application diagrams for these devices. v in = 3.0v v out = 3.0v q1 gate v cc2 setv en gnd r1 r2 v cc1 ADM6819 v in = 3.3 v v out = 3.3 v on off 05133-012 figure 18. ADM6819 applications diagram v in = 3.0v v out = 3.0v q1 gate v cc2 c set setv setd gnd r1 r2 v cc1 adm6820 v in = 3.3 v v out = 3.3 v 05133-013 figure 19. adm6820 applications diagram when the primary supply is above the desired threshold, the ADM6819/adm6820 are designed to control the n-channel fet in the secondary power path to enable the secondary supply. the gate pin is held low while both v cc1 and v cc2 are below the undervoltage threshold, ensuring that the fet is held off. when v cc1 or v cc2 is above uvlo and the primary supply is above the desired level dictated by the resistor divider to the vset pin, the external fet is driven on after the delay has expired. an internal charge pump enhances the external fet. a fet with a low drain-source resistance and low v th should be chosen to reduce voltage drop across the drain-source when the fet is fully enhanced. either supply may act as the primary source if v cc1 or v cc2 is greater that 2.95 v. a decoupling capacitor of typically 100 nf should be used on whichever v cc is the main supply. setv pin the ADM6819/adm6820 enable a supply after a monitored supply voltage exceeds a programmed threshold. this threshold is programmed by a r1/r2 resistor divider on the setv pin. once the voltage on setv exceeds the 0.618 v threshold, the fet switches on after the delay timer expires. on the adm6820, this delay is programmable using a capacitor on the setd pin. on the ADM6819, this delay is fixed at 300 ms and the en pin must be valid high to begin the timer. the required turn-on voltage is calculated by the following equation: r1 = r2 (( vtrip / v th ) C 1) where: vtrip is the minimum turn-on voltage at the supply being monitored. v th = 0.618 v. high value resistors can be used because the setv input current is typically 10 na. en pin the ADM6819 has an enable (en) pin connected to the input of a second comparator, which is identical to that on the vset pin. en can be used as a digital input provided the signal v ol is below 0.6 v. alternatively, the enable input can be used to validate a second supply. the fixed 300 ms timer does not begin counting until both setv and en are above the threshold. as a result, the output is not enabled until this timer has expired. gate pin the internal charge pump is capable of driving the gate of an n-channel mosfet with no external capacitors. this ensures that the mosfet is enhanced to provide a minimum voltage drop across the mosfet, thus reducing the voltage drop across the fet. this charge pump is designed to drive the high imped- ance capacitive load of a mosfet gate input. the gate pin should not be resistively loaded because it reduces the gate drive capability. during undervoltage lockout, gate is held to gnd. setd pin the adm6820 features a capacitor adjustable sequencing delay. a capacitor connected to the setd pin determines the length of the sequencing delay. the sequencing delay can be calculated by the following equation: t delay (s) = 2.652 10 6 cset the ADM6819 has a fixed 300 ms delay.
ADM6819/adm6820 rev. 0 | page 11 of 12 outline dimensions 1 3 4 5 2 6 2.90 bsc 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.22 0.08 10 4 0 0.50 0.30 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.60 0.45 0.30 pin 1 indicator compliant to jedec standards mo-178-ab figure 20. 6-lead small outline transistor package [sot-23] (rj-6) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADM6819arjz-reel7 1 ?40c to +85c 6-lead small outline transistor package [sot-23] rj-6 m2r adm6820arjz-reel7 1 ?40c to +85c 6-lead small outline transistor package [sot-23] rj-6 m2s 1 z = pb-free part.
ADM6819/adm6820 rev. 0 | page 12 of 12 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05113-0-7/06(0)

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